プロフィール詳細

プロジェクトを作成

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Er. Neeraj Nayan P.に依頼

India

VLSI Research Expert | TCAD Simulation | Verilog HDL | Published Reserach Papers | Research M.Tech (VLSI) | B.Tech (ECE)

プロフィール概要

I m a PhD Scholar, Done M.Tech in VLSI Design & Testing with strong expertise in semiconductor device simulation, Verilog HDL, and academic research writing. Done B,Tech in ECE, have knowledge about electronics. I have published research papers in domains such as FinFET, NC-FET, CMOS Inverter, and Tristate Buffers using TCAD tools like Cadence, Visual TCAD and Sentaurus. I also offer Verilog HDL-based FPGA designs and technical writing support, including patent documentation and journal editing. My strengths include FinFET/CMOS design, radiation modeling (TID), and power optimization in digital systems.

専門分野

• ☆ Electrical Engineering
• ☆ Semiconductors
• ☆ Electronics Engineering
• ☆ Electronic Circuits
• ☆ Integrated Circuits/Microchips
• ☆ Microelectronics
• ☆ Publishing

サービス

• Writing
• Research
• Consulting
• Data & AI
• Product Development

Writing Technical Writing

Research Technology Scouting, Scientific and Technical Research

Consulting Scientific and Technical Consulting

Data & AI Data Visualization

Product Development Concept Development, Device Fabrication

職務経験

None

none

1月 2025 - 1月 2025

学歴

M.tech In VLSI Design & Testing

Lovely Professional University

8月 2023 - 7月 2025

認定資格

• VLSI Design with EDA Tools and Reconfigurable Architectures

  LOVELY PROFESSIONAL UNIVERSITY

  1月 2024 - 5月 2024