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プロフィール詳細

プロジェクトを作成

★★★★★

☆☆☆☆☆

★★★★★

☆☆☆☆☆

James S.に依頼

United States

プロフィール概要

Semiconductor design, IC SoC, Artificial Intelligence hardware / software, Machine Learning, AI ML HW SW, Energy Optimization Low Power, Software Development, Electronic Design Automation (EDA), ATPG DFT BIST MBIST LBIST, Static Timing Analysis STA, Logic Equivalence Formal Verification, Transistor-level custom design, Management Executive Leadership, R&D Engineering, Patent Intellectual Property IP

専門分野

• ★ Semiconductors
• ★ Artificial Intelligence
• ☆ Electrical Engineering
• ☆ Computer Hardware
• ☆ Software Engineering
• ☆ Computer Simulation/Computational Modeling
• ☆ Machine Learning
• ☆ Intellectual Property Law
• ☆ Management
• ☆ Innovation Management

サービス

• Consulting
• Data & AI
• Product Development

職務経験

Senior Director R&D

Synopsys Inc

9月 1995 - 5月 2017

Senior Manager, Semiconductor Design Engineering

Standard Microsystems Corporation (SMC)

9月 1982 - 9月 1995

学歴

BS EE, Electrical Engineering

Rensselaer Polytechnic Institute

1月 1978 - 5月 1982

認定資格

• 認定資格の詳細は未入力です。

出版物

PATENT

(2017). Method and apparatus for floating or applying voltage to a well of an integrated circuit. USPTO.

(2016). Placing transistors in proximity to through-silicon vias. USPTO.

(2015). ESD/antenna diodes for through-silicon vias. USPTO.

(2014). Determination of meta-stable latch bias voltages. USPTO.

(2013). Method and apparatus for placing transistors in proximity to through-silicon vias. USPTO.

(2004). Path dependent power modeling. USPTO.

(2004). Apparatus and method for improved precomputation to minimize power dissipation of integrated circuits. USPTO.

(2001). Method and system for pipe stage gating within an operating pipelined circuit for power savings. USPTO.

(2001). Three-dimensional power modeling table having dual output capacitance indices. USPTO.

(2000). Method and system for determining a signal that controls the application of operands to a circuit-implemented function for power savings. USPTO.

(1998). State dependent power modeling. USPTO.

(1988). Video dot intensity balancer. USPTO.

(1987). Virtual ground read only memory. USPTO.

CONFERENCE PAPER

(2004). A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O Signals. International Test Conference, ITC 2004.

(2003). Test Pattern Compression Using Prelude Vectors in Fan-out Scan Chain with Feedback Architecture. Design Automation and Test in Europe Conference, DATE 2003.

(2002). Innovations in Test Automation. 20th IEEE VLSI Test Symposium, VTS 2002.

(2000). Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. Design Automation and Test in Europe, DATE 2000.

CONFERENCE ABSTRACT

(1997). Low power design without compromise (panel). International Symposium on Low Power Electronics and Design, ISLPED 1997.

(1997). Low-power design tools—where is the impact? (panel). Design Automation Conference, DAC 1997.