プロフィール詳細

プロジェクトを作成

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Naveen J.に依頼

India

AI Hardware & VLSI Architect | PhD Researcher | 5 Yrs Exp (Verilog, MATLAB) | Low-Complexity DSP & Neural Nets

プロフィール概要

I am a VLSI Architect and Researcher currently pursuing my PhD at NIT Calicut, specializing in VLSI architectures for Neural Networks. With 5 years of industry experience in automotive engineering and ongoing advanced academic research, I bridge the gap between theoretical AI/DSP algorithms and practical, low-power hardware implementations. Academic Research & Publications: PhD Major Topic: Designing and optimizing hardware architectures for Neural Networks, classifiers, and related Digital Signal Processing (DSP) systems. Publication: Authored "A Novel Low-Complexity Approach to Drowsiness Detection Using One Bit Bayes Classifier," published in ICETCI. Ongoing Review: Two papers are currently in the final review stage for the prestigious Q1 journal IEEE TCAS-I, detailing novel hardware architectures for classifiers and DSP systems. MTech Publication: Developed and published "An embedded musculo-skeletal injury detection system" in ICETT, based on wearable smart dress technology. Industry Experience (Tata Consultancy Services - EIS | 2017–2022): ADAS & Systems Design (3 Years): Developed logic and workflows for Advanced Driver Assistance Systems (ADAS), specifically Automatic Parking Assist (APA), utilizing MATLAB Stateflow and Talend. Hardware Design (2 Years): Specialized in Verilog design, translating complex system-level requirements into robust RTL architectures. Core Competencies & Technical Skills: Hardware Description & Programming: Verilog, VHDL, Python, C, C++, Embedded C, Assembly (ARM/x86/8051), Bare-Metal Programming. Design Methodologies: ASIC Synthesis, FPGA Prototyping, Low-Complexity System Architecture. EDA & Simulation Tools: Cadence Suite (Genus, Virtuoso, Innovus), MATLAB/Stateflow, Talend. Please find a short introduction video (verification) : https://youtu.be/F6WFB3D-Qnk Recent projects: 1. Engineered a custom 13-layer EdgeTextCNN (Mini U-Net) for autonomous vehicle road detection (KITTI Dataset). Utilized frequency-domain preprocessing (Log-Gabor masking) to isolate structural edges, achieving state-of-the-art semantic segmentation optimized for edge hardware deployment. 2. Gemini said Engineered a real-time, 4-stage RTL image denoiser pipeline that utilizes custom SRAM interleaving and optimized 16-bit fixed-point math to deliver edge-preserving smoothing under strict single-port memory constraints.

専門分野

• ☆ Electrical Engineering
• ☆ Semiconductors
• ☆ Electronics Engineering
• ☆ Integrated Circuits/Microchips
• ☆ Signal Processing
• ☆ Data Analysis
• ☆ Image Processing
• ☆ Algorithm Design
• ☆ Machine Learning
• ☆ Deep Learning
• ☆ Computer Vision
• ☆ Applied Mathematics
• ☆ Mathematical Control Theory
• ☆ Differential Equations
• ☆ Pure Mathematics
• ☆ Fractals
• ☆ Number Theory
• ☆ Categorical Algebra
• ☆ Algebra
• ☆ Calculus
• ☆ Mathematical Logic
• ☆ Discrete Mathematics
• ☆ Integral Equations
• ☆ Python
• ☆ Matlab
• ☆ SQL
• ☆ LaTex
• ☆ Counseling & Mental Health Support
• ☆ Body Image

サービス

• Writing
• Research
• Consulting
• Data & AI
• Product Development

Writing Technical Writing

Research Fact Checking, Gap Analysis, Gray Literature Search, Scientific and Technical Research, Systematic Literature Review

Consulting Scientific and Technical Consulting

Data & AI Predictive Modeling, Image Processing, Image Analysis, Algorithm Design-Non ML, Algorithm Design-ML, Data Visualization

Product Development Formulation, Product Validation, Concept Development, Product Launch Support, Packaging Design, Prototyping, Reverse Engineering, Device Fabrication

職務経験

Research Scholar

National Institute of Technology Calicut

1月 2022 - 現在

EIS- Senior System Engineer

Tata Consultancy Services Private Limited

3月 2017 - 1月 2022

学歴

Ph.D

National Institute of Technology Calicut

1月 2022 - 現在

Master of Technology

RIT Government Engineering College, Kottayam, Kerala

6月 2014 - 8月 2016

B.Tech.

Government engineering college BartonHill Trivandrum, Kerala

6月 2009 - 8月 2013

認定資格

• Master of Technology

  Mahatma Gandhi University

  https://drive.google.com/file/d/1ir8chlgyjem25Xi9GBQr5ZhUm8D_x3b1/view?usp=drive_link

  9月 2016 - 現在

• Bachelor of Technology

  Kerala University

  https://drive.google.com/file/d/1S0qACkmXUVorTMTfGtHijWElrkqZgpmd/view?usp=drive_link

  11月 2013 - 現在

出版物

JOURNAL ARTICLE

Naveen Jones, Mekha Mariam Mathew, Unnikrishnan Gopalakrishna Panicker (2025). Self-healing and flexible piezoelectric nanogenerators from sustainable sources: Natural rubber composites empowered by embedded machine learning protocol for real-time remote alert system . Chemical Engineering Journal.

CONFERENCE PAPER

Naveen Jones, M. Surya Prakash, Anup Aprem (2024). A Novel Low-Complexity Approach to Drowsiness detection Using One Bit Bayes Classifier . 2024 International Conference on Emerging Techniques in Computational Intelligence (ICETCI).

Naveen Jones, Manju Manuel, Sreelal Pillai (2016). An embedded musculo-skeletal injury detection system . 2016 International Conference on Emerging Technological Trends (ICETT).